Integrated circuits are used in a wide range of electronic devices produced by a large number of device manufacturers. In practice, ICs are seldom manufactured (fabricated) by the electronic device manufacturer. Instead ICs are manufactured by an IC foundry to the specifications of the electronic device manufacturer. The design of the IC is usually the result of collaboration between the device manufacturer and the IC foundry.
The design and manufacture of an application-specific IC, or ASIC, is usually a long, highly detailed and intensive process, requiring development of a hardware description language (HDL) description of the design, usually in a synthesizable register transfer language (synthesizable RTL), synthesizing the RTL description to a technology library of components, specifying the placement of those components on the silicon platform or on the ASIC die, specifying the physical interconnection of those components, closing the required physical specifications such as functional timing power, area, etc., inserting circuits for manufacturing test, taping out the design, fabricating the circuit into a physical IC chip and testing the chip. Often, tests reveal that re-design is necessary to meet objectives, thereby requiring the process be repeated. The process is time consuming and costly.
To reduce the time and cost of development of ASICs, IC foundries have developed standard, or base, platforms containing silicon layers of an IC, but without some or all of the metal interconnection layers. The silicon layers are configured with metal interconnection into gates that can be configured into cells using tools supplied or specified by the IC foundry. The chip designer specifies designs that are realized using the supplied or specified tools through the addition of additional metal layers for the base platform. This effectively configures the chip into a custom ASIC employing the customer's circuit design and other intellectual property (IP). The IC foundry ordinarily supplies or specifies tools to the IC designer to enable the designer to quickly and accurately configure the base platform to a custom ASIC compatible with the foundry's fabrication technology. An example of such a configurable base platform is the RapidChip® platform available from LSI Logic Corporation of Milpitas, California. The RapidChip platform permits the development of complex, high-density ASICs in minimal time with significantly reduced design iteration, turn around time, manufacturing risks and costs.
One problem in any silicon development process is the effective physical integration of IP. IP is typically developed without regard to the specifics of the physical environment where it will eventually reside. A current approach is to apply margins to the design in hopes that they can be traded off during the physical integration process. One problem with this is that margins are often not representative of the actual problems incurred during physical integration. The result of this is that the physical integration of IP into the IC can be a highly iterative process in a very expensive, time consuming and late portion of the design process.
Each piece of IP has a set of physical characteristics that are associated with it. What is important for one piece of IP may not be for another piece of IP. Consequently, the set of characteristics that are important for one IP may be different from the set of characteristics that are important for another IP.
For example an IP circuit dealing with a defined protocol that operates at a specific frequency must operate at that frequency or it is of no use. However another piece of IP may be useful over a variety of frequency ranges. These frequency ranges are application specific. Other characteristics that may be important to a given IP include area, metal utilization, porosity, congestion etc. This example is illustrative only and there are numerous additional possible characteristics.
The context of a piece of IP is important when physically integrating the IP into a chip design. The context defines how the IP is driven in the chip design and how the characteristics of the integrated (placed) IP affect the IC design. The context is based in part on a specific positioning of the IP in the IC, and different positions for the IP may produce different contexts. Thus, one significant issue its whether or not the IP specific physical requirements can be met, given the context of a physical placement. Another significant issue is the effect that this piece of IP places upon the rest of the design given this context.
It is often the case that changes to the design must be made to achieve the physical implementation that is required. The changes can come in a variety of forms that range from architectural redesign in the RTL stage to altering the physical placement of the design. Any of the alternatives within this continuum of options can lead to multiple expensive iterations and delays.
Designers do not always take into account the environment in which the IP will be placed. For example, a piece of IP that can be placed in an area X if sufficient wiring levels and porosity are available might require a greater area if the IC includes a high content of memory, processor and/or other physical obstructions. Therefore, additional elements must be considered to define the context in which the IP will be used. Moreover, the importance of these elements may vary depending upon the context. Therefore, there is a need for a technique to characterize IP for physical integration into an IC and to selectively define the importance of elements of the characteristics for a given context.